Charge recycling amplifier for a high dynamic range CMOS imager

ABSTRACT

A high dynamic range amplifier circuit for amplifying pixel signals of an imager device is disclosed. The amplifier circuit uses a read-out scheme based on a charge recycling approach, where a pixel signal is first amplified with a low gain during a first amplification phase T 1 , and then the amplifier output is immediately recycled and the pixel signal amplified with a higher gain during a second amplification phase T 2.

This application is a divisional of application Ser. No. 10/222,788, filed Aug. 19, 2002, the subject matter of which is incorporated by reference herein.

FIELD OF THE INVENTION

The invention relates to a charge recycling amplifier within a CMOS imaging device having improved dynamic range.

BACKGROUND OF THE INVENTION

One technique to increase dynamic range of a CMOS active pixel imager is to amplify pixel signals using two separate signal gains. The first applied gain is usually smaller than the second. The two amplified pixel signals are later combined together to produce the actual pixel output signal.

Since the currently adopted column parallel architecture uses a destructive read-out scheme, multiple exposures of the CMOS imager pixel array are required to capture pixel signals for each of the applied gain values. Sampling multiple exposures is a time consuming process, limiting the speed of image capture.

BRIEF SUMMARY OF THE INVENTION

The invention provides a charge recycling amplifier for use in a CMOS imaging device so that only one exposure of the array is required while still producing a pixel signal subject to two different gain values. The charge recycling amplifier comprises a differential amplifier; a pair of input capacitors connected to the inputs of the differential amplifier; first and second pairs of feedback capacitors where each are connected between the input and output of the differential amplifier; a crowbar switch for forcing a charge present on the input capacitors through the differential amplifier; and first and second pairs of gain switches connected to the first and second pairs of feedback capacitors respectively, for setting the gain of the charge recycling amplifier and at least one switch for recycling output charge on a pair of feedback capacitors back to the input of the differential amplifier. A pixel signal presented to the amplifier is first amplified with a first gain setting and then the amplified signal is amplified again with a second gain setting.

In yet another aspect of the invention, a method of operating the above components is disclosed.

These and other features and advantages of the invention will be more clearly seen from the following detailed description which is provided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified block diagram of a CMOS imaging device containing a charge recycling amplifier in accordance with the present invention;

FIG. 2 shows a schematic diagram of the charge recycling amplifier of FIG. 1;

FIG. 2A shows the present invention at a first time during the charge-recycling process;

FIG. 2B shows the present invention at a second time during the charge-recycling process;

FIG. 2C shows the present invention at a third time during the charge-recycling process;

FIG. 2D shows the present invention at a fourth time during the charge-recycling process;

FIG. 2E shows the present invention at a fifth time during the charge-recycling process;

FIG. 3 shows a timing diagram for the circuit of FIG. 2;

FIG. 4 contrasts a simulation output of the present invention with the output of a conventional non-recycling charge amplifier; and

FIG. 5 shows an alternative embodiment of the charge recycling amplifier of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a dual gain system based on a charge recycling approach, to eliminate the need for obtaining two pixel signals from the array. With the present invention, the signal charge is first amplified at low gain during an initial amplification phase T1, and then the same charge is immediately re-used or recycled within an amplifier for a high gain amplification which occurs during phase T2. This approach eliminates the need to resample the pixel signal and reset the amplifier between the two signal gains. Since the high gain signal is readily available at the clock cycle following the low gain amplification, a considerable speed advantage occurs. Also, implementing the present invention requires only minimal variations to currently used pixel read-out schemes.

FIG. 1 shows a block diagram of a CMOS imaging device that uses the fully differential charge recycling analog amplifier in accordance with the present invention. In FIG. 1, a CMOS image search array 20 passes pixel reset and image signals from rows of pixels in the array connected to a column line to a sample and hold circuit 40, which in turn is connected to the charge recycling amplifier (CRA) 200. The CRA 200 passes image information to an analog/digital converter 60, which in turn passes digital information to an image processor 80, which then outputs signals representing a digitized image.

FIG. 2 is a schematic diagram of the CRA 200. It includes a fully differential charge mode amplifier 204 having input capacitors Cin on the input path and a crowbar switch p1 for coupling together the input sides of the input capacitor cin. The appropriate gain of the CRA 200 (low and high) is selected by switch pairs g1 and g2 responsive to a controller 202. The switch pair g1 is always operated simultaneously, as is the switch pair g2. For simplicity, FIG. 2 shows only two separate pairs of feedback capacitors Cf1 and Cf2, although additional pairs could be added as shown in FIG. 5 and described below. An additional set of serially connected switches g3 is connected across Nodes A and B. The switches g3 are fabricated as a pair of simultaneous switches rather than single switch to maintain circuit balance and reduce the amount of current leakage during the charge recycling process, and are used to force charge stored across the feedback capacitors Cf1 back into the input nodes 208 of the charge mode amplifier 204 during a second stage of amplification. Reset switches p2 are provided in the amplifier feedback path to reset the differential amplifier 204 between charge sampling operation. All switches are responsive to output control signals from the controller 202.

It is important to note that the upper half of the CRA 200 is fabricated to be as symmetrical as possible with its lower half. In other words, for the CRA to operate properly, the upper capacitor Cf1 must equal the lower capacitor Cf1, the upper capacitor Cf2 must equal the lower capacitor Cf2, and the upper input capacitor Cin must equal the lower input capacitor Cin. Henceforth all references to these elements will be understood to apply to the pair of elements and not to a single element.

The gain of the CRA 200 is determined by a ratio of the input capacitor Cin to the feedback capacitance. Since the feedback capacitance can be changed by selectively switching Cf1 and Cf2 in circuit, gain can likewise be changed.

A timing diagram depicting the operation of the CRA 200 is shown in FIG. 3, where T1 has a duration of exactly one clock cycle, as does T2. At the beginning of the time period T1, the reset switch p2 is opened, while the gain switches g1 and g2 remain closed, as shown in FIG. 2A. This corresponds to a low gain phase of operation denoted as T1. During the low gain operational phase T1, the gain of the amplifier 200 is:

Gain1=Cin/(Cf 1+Cf 2)  (1)

Shortly after the beginning of the lower gain amplification phase T1, as shown in FIG. 2B the crowbar switch p1 is closed so that pixel reset and image signal charges previously respectively sampled onto the input capacitors Cin is driven into the amplifier circuit. The reset and image signals are received by the differential amplifier 204 and amplified at the output nodes Vout+ and Vout−. Just before the end of the first lower gain amplification phase T1, the output signal of the CRA 200 settles within the desired accuracy and is read out to the analog to digital converter 60.

At the onset of the second (higher gain) amplification phase T2, the gain select switches g2 are opened (FIG. 2C), which puts the amplifier into high-gain mode since the gain of the amplifier now becomes:

Gain2=Cin/Cf 2  (2)

During the amplification phase T2, a voltage Vav is created at node A and node B of the CRA 200. Vav is the common mode voltage of the signal which corresponds to the output signal of the CRA output lines Vout− and Vout+. Applying a voltage Vav while the pair of switches g2 is opened causes the charge stored on the capacitors Cf1 to flow back into the input nodes 208 of the differential amplifier 204. That charge is thus recycled for use in the higher gain amplification phase T2. The best way to force the nodes A and B to the common mode voltage Av which is forced back through amplifier 204 is by shorting them together through the pair of switches g3, as shown in FIG. 2D. By closing the switches g3, the average voltage value generated is

Vav=(Vout−+Vout+)/2  (3)

which corresponds to a common mode voltage signal. Closing the switches g3 forces the CRA 200 to recycle the charge sampled on the feedback capacitors Cf1. During the higher gain amplification phase T2, only the incremental amount of charge stored across the capacitors Cf1 is redistributed into the input node 208 of the differential amplifier 204. This has the advantage of increasing the speed of operation of the CRA 200.

Just before end of the second higher gain amplification phase T2, the output signal of the CRA 200 has settled within the desired accuracy and is read out. At the end of the phase T2, which coincides with the beginning of the reset phase T3, the switch pair g1 is opened and the differential amplifier 204 is reset by closing the pair of switches p2 as shown in FIG. 2E.

This provides a differential pixel output signal at Vout+ and Vout1 which has a higher gain than the pixel output signal produced during the T1 phase.

Because of this recycling, it is not necessary to reacquire pixel data on the input capacitors Cin. Instead, charge information present on the capacitors Cf1 can be reused, so that only a single exposure of the CMOS imager 20 (FIG. 1) is necessary. Thus, the CRA 200 accomplishes a non-destructive readout of the originally applied pixel signal while providing sequential outputs of the differentially amplified pixel reset and image signals first at a lower and then at a higher gain. The read-out is termed non-destructive because the reset and image signals on the capacitors C_(IN) is not lost after the first amplification stage, but is instead recycled.

FIG. 4 contrasts a simulation output 404 of the CRA 200 of the present invention with a higher gain output 408 of a non-recycling charge amplifier output of the prior art. The output 404 of the CRA 200 reaches its quiescent point in two stages T1 and T2, while the output 408 of the non-recycling amplifier reaches its quiescent point in a single stage. However, from FIG. 4 it is apparent that the two signals 404 and 408 end up being duplicates of each other after time period T2. Accordingly, no unwanted artifacting nor loss of charge occurs when using the CRA of the present invention.

The charge recycling technique of the present invention can be expanded by adding more pairs of feedback capacitors Cf3, Cf4 . . . Cfn as shown in FIG. 5 to allow for different selection of gain values during the T1 phase in accordance with equation (1) above whereby the capacitance values of the capacitor switched in circuit during the T1 phase set the value of the denominator.

In addition, the FIG. 5 amplifier can be further modified as shown by doted lines to permit further recycling in a third phase T3 by using the voltage on a pair of capacitors Cf4 existing after the second phase T2. Thus, the charge on the capacitors can then be recycled following stage T1 through in successive stages T2 and T3. In such an arrangement, each phase would have an increasingly higher charge gain. This technique can also be repeated for additional stages, e.g. T4, etc.; however, once the output voltage of the differential amplifier 204 reaches its saturation, a considerably higher gain error is introduced, the inverting node 208 of the amplifier 204 is no longer at virtual ground, and no more meaningful charge recycling can be expected. Accordingly, this sets a limit on the number of gain stages T1, T2, T3 etc., which can be used.

Because of charge recycling, it is not necessary to re-acquire pixel data on the input capacitor Cin. Instead, charge information present on the capacitors Cf1 can be re-used, so that only a signal exposure of the CMOS imager 20 (FIG. 1) is necessary. Thus the CRA 200 accomplishes a non-destructive readout of the originally applied pixel signal while providing sequential output of the amplified pixel signal first at a lower and then at a higher gain.

While the invention has been described and illustrated with reference to specific exemplary embodiments, it should be understood that many modifications and substitutions can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the appended claims. 

What is claimed as new and desired to be protected by Letters Patent of the United States is:
 1. A pixel processing circuit, comprising a sample and hold circuit for sampling a reset signal and a pixel image signal from a pixel; and a charge recycling differential amplifier for receiving the output from said sample and hold circuit, said charge recycling differential amplifier first differentially amplifying said reset signal and pixel image signal with a first gain and providing a resulting first output signal during a first operational phase and then differentially amplifying said reset signal and pixel signal with a second gain and providing a second resulting second output signal during a second operational phase.
 2. A pixel amplifying system comprising: a sample and hold circuit for receiving at least one signal from said pixel; an amplifier for receiving a signal from said sample and hold circuit; a first circuit arrangement associated with said amplifier for operating said amplifier to amplify a signal received from said sample and hold circuit with a first gain value to produce a first pixel output signal; and a second circuit arrangement associated with said amplifier for operating said amplifier to amplify the signal received from said sample and hold circuit with a second gain value to produce a second pixel output signal.
 3. A method of amplifying a pixel signal, said method comprising: capturing said pixel signal; amplifying said captured pixel signal with a first gain value to produce a first amplified pixel output signal; and amplifying said captured pixel signal with a second gain value to produce a second amplified pixel output signal.
 4. The method of claim 3 further comprising amplifying at least a portion of said first amplified output signal to produce said second amplified pixel output signal. 